Auto gain control (AGC) refers to a technique to make a reception level which varies due to communication distance between a base station apparatus (hereinafter abbreviated as “base station”) and a communication terminal apparatus (hereinafter abbreviated as “terminal”) or fading stable in order to improve demodulation accuracy.
FIG. 1 is a block diagram of a principal-part configuration of a receiving section of a typical terminal which performs conventional auto gain control. In FIG. 1, receiving section 10 has variable gain amplifying section 11, AD (Analog-to-Digital) converting section 12, AGC control section 13 and demodulating section 14. In addition, for ease of description, in FIG. 1, a frequency converting section that converts a frequency band of a received signal and an IQ demodulating section that extracts signals of I signal and Q signal from received signals are not illustrated.
In FIG. 1, variable gain amplifying section 11 receives an input of a signal received at an antenna, and adjusts the gain of the received signal according to a gain setting value outputted from AGC control section 13. AD conversion section 12 converts the received signal of the adjusted gain, into a digital signal. Demodulating section 14 demodulates the digital signal to acquire received data. AGC control section 13 generates an adequate gain setting value according to the digital signal and target power, and outputs the generated gain setting value to variable gain amplifying section 11.
FIG. 2 is a block diagram illustrating a configuration of AGC control section 13. AGC control section 13 shown in FIG. 2 has signal power detecting section 21, gain error calculating section 22, gain computation value calculating section 23, LPF (Low Pass Filter) 24 and gain setting value storing section 25.
In AGC control section 13 employing the configuration illustrated in FIG. 2, signal power detecting section 21 calculates average signal power of the AD converted digital signal in a predetermined period. Gain error calculating section 22 calculates gain error based on average signal power and target power. Hereinafter, the gain error refers to the difference between a present gain setting value calculated from the magnitude of a received signal (average signal power) and an ideal gain setting value calculated from target power. When units of average signal power and target power are represented by dB, the gain error (dB) is obtained by calculating the difference between average signal power and target power. Gain computation value calculating section 23 calculates a gain computation value based on the gain error and gain setting value outputted from gain setting value storing section 25, and outputs the calculated gain computation value to LPF 24. LPF 24 prevents an abrupt change of gain by applying LPF processing to the gain computation value, and outputs the acquired gain computation value as a gain setting value.
By performing the above operation, AGC control section 13 adjusts a gain setting value according to the magnitude of the received signal. By this means, receiving section 10 can perform adequate signal receiving processing.
Features which this AGC control requires include to improve the accuracy of gain (that is, accuracy of convergence) upon gain convergence, and to reduce the time for gain convergence.
By increasing a time constant of LPF or increasing a gain update cycle, the degree of change of gain becomes small and the gain is followed moderately, so that it is possible to accurately calculate average signal power. Consequently, it is possible to improve the accuracy of convergence of gain. A mode which increases a time constant of LPF or increases a gain update cycle to make the degree of change of gain small and moderately follow gain, is referred to as “tracking mode” or “low speed AGC mode.” With the tracking (low speed AGC) mode, a time constant of LFP is increased or gain update cycle is increased, and therefore it takes time until the gain converges.
By contrast, by decreasing the time constant of LPF or decreasing a gain update cycle, a gain can be converged in a shorter time. A mode which can converge a gain quickly in a shorter time is referred to as “pull-in mode” or “high speed AGC mode.” With the pull-in (high speed AGC) mode, although it is possible to converge a gain in a shorter period, the gain follows the rapid change of the amplitude of a received signal, and therefore gain convergence accuracy degrades.
Generally, a gain setting with respect to the magnitude of a received signal is out of an adequate state when reception starts. Therefore, when reception starts, the gain convergence time is reduced using the high speed AGC mode. Further, a method is adopted which improves gain convergence accuracy by converging a gain to some extent and then switching to the low speed AGC mode (see, for example, Japanese Patent Application Laid-Open No. 2002-290177).
By the way, signals defined by 3GPP include Fish Bone Effect (FBE) signals. An FBE signal has a period in which instantaneous power of a received signal rapidly becomes smaller than average power (hereinafter “FBE signal period” or “low power period”).
Hereinafter, the FBE signal and FBE signal period will be described.
FIG. 3 illustrates a channel configuration of a downlink common channel defined by 3GPP (see 3GPP TS 25.211 V9.1.0 (2009-12) and 3GPP TS 25.213 V9.1.0 (2009-12)). In FIG. 3, P-CPICH (Primary Common Pilot Channel) is a channel utilized for channel estimation, cell search and a timing reference for other downlink physical channels in the same cell in a terminal, and is a channel for transmitting a so-called pilot signal. Further, P-CCPCH (Primary Common Control Physical Channel) is a channel which exists in each cell, and which is used to transmit broadcast information.
As illustrated in FIG. 3, one frame has 15 time slots. The slot length of each time slot is 2560 chips (667 μs). As illustrated in FIG. 3, P-CPICH is used as a reference for other channels.
P-CPICH, the spread factor of P-CCPCH and channelization code No. are each defined as follows.
The spread factor (SF) of P-CPICH is 256, and channelization code No. is 0.
The spread factor (SF) of P-CCPCH is 256, and channelization code No. is 1.
Channelization code No. 0 is a spread code of 1 at all times, and channelization code No. 1 is a spread factor of 1 for the first half of 128 chips and −1 for the second half of 128 chips.
Further, IQ data of P-CPICH is (1, 1) at all times, and IQ data of P-CCPCH is four types of (1, 1), (1, −1), (−1, −1) and (−1, 1).
The base station transmits a downlink common channel in which the above P-CPICH and P-CCPCH are multiplexed. The downlink common channel formed when channel powers of P-CPICH and P-CCPCH are equal is represented as follows.Downlink common channel=(PCPICH data×channelization code No. 0+PCCPCH data×channelization code No. 1)×scrambling code=downlink common channel signal point×scrambling code
According to a combination of the above IQ data and spreading code, the signal point of the downlink common channel adopts one of (2, 2), (2, 0), (0, 2) and (0, 0). Of these signal points, the e rate that (2, 2) is adopted is 25%, the rate that (2, 0) or (0, 2) is adopted is 50% and the rate that (0, 0) is adopted is 25%. Further, of these signals points, (2, 2) has the greatest signal power, (2, 0) or (0, 2) has the second greatest power and (0, 0) has the least signal power.
The signal power of the downlink common channel having these signal points vary according to the following variation pattern.
Variation Pattern [1]:
When the first half of 128 chips of one symbol (256 chips) has signal power [high] (that is, signal point (2, 2)), the second half of chips has signal power [low] (that is, signal point (0, 0)).
Variation Pattern [2]:
When the first half of 128 chips of one symbol (256 chips) has signal power [low] (that is, signal point (0, 0)), the second half of chips has signal power [high] (that is, signal point (2, 2)).
Variation Pattern [3]:
When the first half of 128 chips of one symbol (256 chips) has signal power [middle] (that is, signal point (2, 0) or (0, 2)), the second half of 128 chips also has signal power [middle] (that is, signal point (2, 0) or (0, 2)). That is, signal power [middle] continues in one symbol (256 chips) unit.
Consequently, when signal power varies in the j-th (j is an integer) symbol according to the variation pattern [1] and signal power varies in the (j+1)th symbol continuing to the first symbol in the time domain according to the variation pattern [2], the period of signal power [low] continues for 256 chips.
The period in which signal power [low] continues for 256 chips and the period in which signal power [low] continues for 128 chips according to the variation patterns [1] and [2] are referred to as “FBE signal period.” In addition, the FBE signal shows the state of signal power [high] in 128 chips before and after the FBE signal period of continuous 256 chips, and one of 128 chips before and after the FBE signal period of continuous 128 chips, and has characteristics that signal power is higher than average signal power.
FIG. 4 illustrates an example of signal power transition of an FBE signal. As illustrated in FIG. 4, in environment in which only the downlink common channel including P-CPICH and P-CCPCH is transmitted, the FBE signal period in which signal power rapidly becomes low is one symbol (256 chips=66.7 μs) or ½ symbol (128 chips=33.3 μs). This FBE signal period is shorter than a cycle (1 slot=2560 chips=667 μs) defined by a target gain, and the FBE signal period in which signal power rapidly becomes low is longer than a gain update cycle (16.67 μs).
FIG. 5 illustrates how a gain changes when a conventional high speed AGC technique is applied as is to FBE signals having these characteristics. In this case, the AGC control section follows the variation of power in the FBE signal period, and the controlled gain is significantly shifted from the target gain.
Further, if the AGC control section is operated in the low speed mode by, for example, sufficiently increasing a gain update cycle than the FBE signal period to prevent the AGC control section from following power variation in the FBE signal period, the gain does not converge in a required time.
In the high speed mode, a receiving apparatus which receives signals which varies abruptly signal power is disclosed in, for example, Japanese Patent Application Laid-Open No. 2000-183765. The receiving apparatus disclosed in Japanese Patent Application Laid-Open No. 2000-183765 holds a gain when power of the received signal varies abruptly.